1. Field of the Invention
The present invention relates to a clock generator and an Organic Light Emitting Display (OLED) including the clock generator, and more particularly, to a clock generator which generates clock signals at high speed without a delay time and without feedback of the clock signals, and to an OLED including the clock generator.
2. Description of the Related Art
In recent years, a high-speed serial link system has become strongly relied upon. Above all, an oscillator used for a transmission terminal and a receiving terminal is one of the most important components of the high-speed serial link system.
FIG. 1 is a circuit diagram of a clock generator. Referring to FIG. 1, the clock generator includes four transistors MP1, MP2, MN1, and MN2, n switching units 10, and an inverter 20.
The transistor MP1 is connected between a high-level voltage line VDD and a node A and is turned on/off in response to a clock signal CLK fed back to the transistor MP1.
The transistor MP2 is connected between the high-level voltage line VDD and a node N and is turned on/off according to the level of the node A. The transistors MP1 and MP2 are P-type Metal Oxide Semiconductor (PMOS) transistors, each of which is turned on in response to a low-level control signal and turned off in response to a high-level control signal.
The transistor MN1 is connected between a low-level voltage line VSS and a node B and is turned on/off in response to a clock signal CLK fed back into the transistor MN1.
The transistor MN2 is connected between the low-level voltage line VSS and the node B and is turned on/off according to the level of the node B. The transistors MN1 and MN2 are N-type Metal Oxide Semiconductor (NMOS) transistors, each of which is turned off in response to a low-level control signal and turned on in response to a high-level control signal.
The n switching units 10 are connected between the node A and the node B. The switching units 10 receive n control signals D1-DN (refer to FIG. 3) with the same delay time and perform a switching operation so that the node A is connected to or disconnected from the node B. The detailed construction of each of the switching units 10 is illustrated in FIG. 2.
FIG. 2 is a detailed circuit diagram of a switching unit of the clock generator of FIG. 1. Referring to FIG. 2, the switching unit 10 of the clock generator includes two transistors MN3 and MN4 and three inverters 21, 22, and 23.
The transistor MN3 is connected to the node A and is turned on/off in response to a first control signal D1.
The transistor MN4 is connected between the transistor MN3 and the node B and is turned on/off in response to a control signal output from the three inverters 21, 22, and 23 that are connected in series. The transistors MN3 and MN4 are NMOS transistors.
The three inverters 21, 22, and 23 that are connected in series receive the first control signal D1 and invert the first control signal D1 three times. Therefore, the first control signal D1 is not transmitted to the transistors MN3 and MN4 at the same time but rather is transmitted to the transistor MN4 after being delayed by a predetermined time due to the serially connected inverters 21, 22, and 23.
Referring to FIG. 1 again, the inverter 20 is connected between the node N and an output terminal and inverts the level of the node N.
Hereinafter, the operation of the clock generator of FIGS. 1 and 2 is described below with reference to FIG. 3.
FIG. 3 is a timing diagram of n control signals, which illustrates the operation of the clock generator of FIG. 1.
Referring to FIG. 3, the n+1 control signals D0-DN are respectively sequentially supplied to the n+1 switching units 10, with a predetermined delay time. Each of the control signals D0-DN has a duty ratio of 50% and alternates between a high level and a low level.
When a clock signal CLK is at a low level and the control signal D1 transitions to a high level, the transistor MP1 of FIG. 1 is turned on, and the transistor MN1 of FIG. 1 is turned off. Thus, a high-level voltage VDD is supplied to the node A.
Also, the transistor MN3 of the switching unit 10 shown in FIG. 2 is turned on, and the transistor MN4 is turned on for a Δ delay time and then turned off. That is, the transistor MN3 is connected to the transistor MN4 (i.e., the node A is connected to the node B) for the Δ delay time, so that the transistor MN2 is turned on in response to a high-level control signal and supplies a low-level voltage VSS to the node N. The low-level voltage VSS is inverted by the inverter 20 and becomes a high-level clock signal CLK. After an elapse of the Δ delay time, since there is no current path between the node A and the node B, no further displacement occurs.
While the n+1 control signals D0 to DN are sequentially supplied, the above-described operation is repeated to generate the clock signal CLK.
As described above with reference to FIGS. 1 through 3, the clock generator structurally uses a feedback signal loop. In this case, since the clock generator operates using an oscillator including an odd number of inverters for a time period in which the feedback signal loop is used, there is a maximum allowed Δ delay time. In addition, there is a minimum allowed time for which both the transistors MN3 and MN4 are turned on at the same time to allow sufficient operation. Furthermore, there is a minimum time taken for a feedback signal to finish a unit operation. As a result, since the clock generator uses a feedback loop, a frequency at which the clock generator outputs a clock signal is limited below 1 GHz.